Dr. Dimoulas is Research Director at NCSR DEMOKRITOS in Athens and head of the MBE laboratory since 1999; presently he has an appointment as LANEF 2016 Chair of Excellence at CEA-INAC. He received his BSc and PhD degrees from the U. of Athens and the U. Crete in Greece, respectively and he served as an EU Human Capital & Mobility fellow at the U. Groningen, Holland and research associate at CALTECH and the U. Maryland College Park, USA. He has also been a visiting research scientist at the IBM Zurich research lab in 2006 and 2007. He has coordinated several EU research projects on high-k gate dielectrics and high mobility semiconductors (Ge, InGaAs) for advanced CMOS. Since 2011, his research focuses on 2D materials (graphene, silicene, germanene and transition metal dichalcogenides) for power scaling of nanoelectronic devices and has received the ERC Advanced Grant SMARTGATE for this work. He has served as general chair of INFOS 2007 conference and TPC chair of ESSDERC 2009 as well as Process Technology subcommittee chair of IEDM 2012. He has numerous technical publications and invited conference presentations and he is the co-editor of a Springer book on “High-k gate dielectrics” and a recently published (2016) CRC press book on “2D Materials for Nanoelectronics”.
Performance improvements across all application domains are now severely limited by the energy dissipation involved in processing and storing information. New materials and device architectures are required for power scaling of nanoelectronic devices. Negative capacitance FETs  is an example of steep slope switches which can operate in the subthermionic regime with a subthreshold slope less than the thermal Boltzmann limit of 60 mV per decade and low power supply voltages in the 100 mV scale. In this presentation, the recent developments  will be reviewed regarding ferroelectric NCFETs. Subsequently, novel metal-insulator-semiconductor capacitors with graphene-encapsulated gates will be presented providing evidence for negative quantum capacitance contributions due to exchange interaction and electron correlation effects in graphene . With the help of device modeling we conclude that our graphene-based devices possess internal gate amplification showing the prospect for the realization of energy efficient negative capacitance FETs.
Acknowledgements: Work funded by ERC Advanced Grant SMARTGATE-291260
References:  S. Salahuddin and S. Datta, Nano Lett. 8, 405(08);  K.S. Li et al., IEDM 2015, 22.6.1;  P. Tsipas et al., Adv. Electron. Mater. 2, 1500297 (16)