Sorin Cristoloveanu received the PhD (1976) in Electronics and the French Doctorat ès-Sciences in Physics (1981) from Grenoble Polytechnic Institute, France. He is currently Director of Research CNRS. He also worked at JPL (Pasadena), Motorola (Phoenix), and the Universities of Maryland, Florida, Vanderbilt, Western Australia, and Kyungpook (World Class University project). He served as the director of the LPCS Laboratory and the Center for Advanced Projects in Microelectronics, initial seed of Minatec center. He authored more than 1,100 technical journal papers and communications at international conferences (including 160 invited contributions). He is the author or the editor of 28 books, and he has organized 25 international conferences. His expertise is in the area of the electrical characterization and modeling of semiconductor materials and devices, with special interest for silicon-on-insulator structures. He has supervised more than 80 PhD completions. With his students, he has received 13 Best Paper Awards, an Academy of Science Award (1995), and the Electronics Division Award of the Electrochemical Society (2002). He is a Fellow of IEEE, a Fellow of the Electrochemical Society, and Editor of Solid-State Electronics.
Recently proposed feedback-FETs with ‘band modulation’ schemes are conceptually different from MOSFETs or TFETs. They have similar gated-diode configuration as TFETs, but are operated in forward-bias mode. Electrostatic barriers are formed (via gate disposition and biasing) to prevent electron/hole injection into the channel until the gate or drain bias reaches a turn-on value. Due to band modulation along the channel and positive feedback mechanism, the device switches abruptly (< 1 mV/decade) from OFF state with low leakage current to ON state with high drive current. The family of feedback barrier-modulation devices includes several SOI designs: • Field-effect diode (FED) with two adjacent top gates, • Thyristor-like structure with specific body doping partition and control via ground-plane bias, • Z2-FET (zero swing and zero impact ionization FET) which has an underlapped top gate and additional control from the ground plane. • Z3-FET (zero gate, zero swing and zero ionization) with free surface and controlled by two ground planes. We will discuss in detail the device physics, architecture, and applications for the most promising variants (Z2-FET and Z3-FET). They feature a large hysteresis useful for single-transistor DRAM and SRAM cells, fast logic, ESD protection and sensing.